library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity any_even is
generic(data_width : integer := 20 );
port
(   input1 : in std_logic_vector(data_width - 1 downto 0);
    clk_in : in std_logic;
   clk_out : out std_logic
	     );
end entity any_even;
 
architecture div1 of any_even is

signal clk_outQ : std_logic ;
signal    coutQ : std_logic_vector (data_width - 1 downto 0);
begin
--------------------------------------------------------- 
process(clk_in)
  begin
     if clk_in'event and clk_in = '1' then
        if coutQ < (conv_integer(input1) - 1) then
            coutQ <= coutQ + 1;
        else coutQ <= (others => '0');
        end if;
     end if;   
end process;
--------------------------------------------------------
process(coutQ)
  begin
     if coutQ < (conv_integer(input1))/2 then
        clk_outQ <= '1';
     else clk_outQ <= '0';
     end if;
end process;
clk_out <= clk_outQ;
end architecture div1;   
